Authors: Chung-Ping Chen, C.C.N. Chu, D.F. Wong

Link to full paper: https://ieeexplore.ieee.org/document/743080


Preliminaries

Define

  • to be the driver resistance for the th input driver, .
  • to be the load capacitance of the th output load, .

A gate, wire segment or an input driver is referred to as a component. We add two factitious components to our circuit:

  1. An output component which consists of all output loads.
  2. An input component which consists of all input drivers. We refer to the connection point two components as a node. We also treat the output point of our output component as a node. There are components and nodes, where is the number of gates or wire segments.

Label the nodes , where , in reverse topological order. That is, index 0 is the output point of the output component and index for is the node connecting to the th output load. For , the node with index is the connection among the gates and wire segments. By this ordering, if node is connected to the input and node is connected to the output, then . We also index the components if the output is connected to node .

center

Define

  • to be the set of indexes of components directly connected to the input(s) of component .
  • to be the set of indexes of components directly connected to the output of component .
  • to be the set of indexes of gates
  • to be the set of indexes of wire segments
  • to be the set of indexes of input drivers
  • For , let be the gate size, the output resistance, and the input capacitance of the pin (we assume all pins share the same input capacitance).
  • For , let and be the unit size output resistance and input capacitance per unit size of gate , i.e., and .
  • For , is the segment width.
  • For , let , and be the unit width wire resistance, the wire area capacitance per unit width and the wire fringing capacitance of segment . Then for wire , and .
  • For , define and such that .

Components are modeled as RC circuits. This allows the use of Elmore delay model for delay calculation. Elmore delay along a signal path is calculated as the sum of the delays associated with the resistors in the path. Each component (exluding the two facitious components) is assumed to contain a resistor . For input driver , we define , i.e., the driver resistance of the th input driver (the is to get it in the right index. Recall is in . Each is offset by indices due to the labeling. Basically we are setting the resistance to that input drivers resistance.)

Let be the downstream capacitance of resistor . In short, the downstream capacitance of a resistor is given by the total capacitance of everything “downstream” resistor . For instance, in the figure below the downstream of capacitance of is as capacitors and are downstream of . But the downstream capacitance of is just .

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The Elmore delay associated with resistor is calculated by . Thus, if a signal path passes through resistors , then the Elmore delay along is given by

We denote the set of all possible paths from node to node 0 by , i.e., any is a path from an input driver to an output load.

Minimizing Total Area Subject to Maximum Delay Bound

Define to be the maximum delay form any input driver to any output load, i.e., is a bound on the arrival time at node . We wish to minimize the total component area, which can be computed by where are some constants. Thus, the problem is

However, there are exponentially many paths. So they partition the path delay constraints into constraints on component delay to form the primal problem:

The constraints for are as follows:

  1. Every input of our factious output component arrives no later than
  2. The arrival time of component cannot be earlier than its inputs with delay from component : .
  3. The arrival time of our input drivers is no less than the input driver’s delay
  4. Size constraints for components.

They relax constraints 1-3 to get the Lagrangian relaxation

where

Notice that the Lagrangian has two variables: component sizes and arrival times .

They use Kuhn-Tucker conditions to show that in order for the optimal solution, , for to also be the optimal solution for one needs for all (to ensure is a saddle point). That is, where

This results in a simpler problem which eliminates variables :

where

and

Lemma 1

For any , the optimal for is the same as the optimal for .

This leaves the following solving strategy:

  1. Solve to find the optimal
  2. Find the optimal by setting to be the smallest possible value that satisfies the constraints of .

Solving

Define

  • to be the set of resistor indexes (excluding ) on the path(s) from component to the nearest upstream gate(s) or input driver(s). For instance, in Figure 2 above: .
  • , i.e., the weighted upstream resistance of component .
  • Modified downstream capacitance:

The phrase local re-sizing of component refers to changing while keeping the sizes of all other components fixed. The optimal local resizing of component minimizes .

Lemma 2

Let be a component-sizing solution. An optimal local re-sizing of component is given by changing the size of component to where and .

No proof for Lemma 2 is provided. Expression is found by minimizing while only changing component .

Their algorithm is a greedy algorithm that iteratively re-sizes each component. In each iteration, each component is examined in order and re-sized optimally using Lemma 2 while keeping the other components fixed. The algorithm then recomputes and incrementally by traversing the circuit in reverse topological order followed by topological order.

Algorithm 9 SOLVE_LRS/μ\textup{SOLVE\_LRS}/\mu

for i=1ni=1\dots n do

xi:=Lix_i := L_i

end for

// Compute CiC_i' for 1in1\le i\le n by traversing the circuit in reverse topological order

for i=1ti=1\dots t do

Ci:={CiLif iGCiL+fi/2if iWC_i' := \begin{cases} C_i^L & \text{if }i\in\mathcal{G} \\ C_i^L + f_i/2 & \text{if }i\in\mathcal{W} \end{cases}

end for

for i=t+1ni=t+1\dots n do

Ci:={0if iGfi/2if iWC_i' := \begin{cases} 0 & \text{if }i\in\mathcal{G} \\ f_i/2 & \text{if }i\in\mathcal{W} \end{cases}

for all kk s.t. iinput(k)i\in input(k) do

Ci:={Ci+ck^xkif kGCi+ck^xk+fk/2+Ckif kWC_i' := \begin{cases} C_i' + \hat{c_k}x_k & \text{if }k\in\mathcal{G} \\ C_i' + \hat{c_k}x_k + f_k/2 + C_k' & \text{if }k\in\mathcal{W} \end{cases}

end for

end for

// Compute RiR_i and xix_i for 1in1\le i\le n by traversing the circuit in a topological order

for i=n1i=n\dots 1 do

Ri:=0R_i:=0

for all jinput(i)j\in input(i) do

Ri:={Ri+μjrj^/xjif jGRi+μjrj^/xj+Rjif jWRi+μjRjnDif jDR_i := \begin{cases} R_i + \mu_j\hat{r_j}/x_j & \text{if }j\in\mathcal{G} \\ R_i + \mu_j\hat{r_j}/x_j + R_j & \text{if }j\in\mathcal{W} \\ R_i + \mu_jR_{j-n}^D & \text{if }j\in\mathcal{D} \end{cases}

end for

xi:=min(Ui,max(Li,μiri^Ci/(ci^Ri+αi)))x_i:=\min\left(U_i,\max\left(L_i,\sqrt{\mu_i\hat{r_i}C_i'/(\hat{c_i}R_i+\alpha_i)}\right)\right)

end for

If there was an improvement, goto line 5

The main aspect of the algorithm is on line 20 when we apply Lemma 2 to component . Lines 5-13 are simply walking along the circuit from right-to-left and keeping track of the downstream capacitance. Lines 16-19 are simply summing up the resistance from each input to the component. The component sizes and resistances are computed left-to-right.

The algorithm runs in time using memory, where is the number of sizable components and is the number of iterations.

Theorem 1

For any fixed vector , algorithm always converges to the optimal component-sizing solution of the problem

Again they claim this with no proof.

Solving the Lagrangian Dual

Define

They consider the Lagrangian dual problem:

They use subgradient optimization method to solve . See Lagrangian Relaxation for more details. In summary, the algorithm works as follows:

  1. Iteration 0: Start from an arbitrary
  2. Step :
    1. Solve (by solving ).
    2. For each relaxed constraint , compute the subgradient . For instance, for constraint the subgradient is where is the value given by our current solution .
    3. Set , where and is some step size.
    4. Project to the nearest point in .

They don’t specify the step size, the simplest would be . The only real requirement for convergence is that and .

Algorithm 10 SOLVE_LDP\textup{SOLVE\_LDP}

k:=1k:=1, λ:=arbitrary entry in Ωλ\lambda:=\text{arbitrary entry in }\Omega_\lambda

while (i=1nαixiQ(λ))ϵ(\sum_{i=1}^n\alpha_ix_i - Q(\lambda)) \le \epsilon do

μ:=(μ0,,μn+s)\mu:=(\mu_0,\dots,\mu_{n+s}) where μi=jinput(i)λji\mu_i=\sum_{j\in input(i)}\lambda_{ji}

Solve LRS/λ\mathcal{L}\mathcal{R}\mathcal{S}/\lambda via SOLVE_LRS/μ\textup{SOLVE\_LRS}/\mu and then calculating a1,,an+sa_1,\dots,a_{n+s}

for i=0,,n+si=0,\dots,n+s do

for all jinput(i)j\in input(i) do

λji:={λji+ρk(ajA0)if i=0λji+ρk(aj+Diai)if iGWλji+ρk(Diai)if iD\lambda_{ji} := \begin{cases} \lambda_{ji} + \rho_k(a_j-A_0) & \text{if } i=0 \\ \lambda_{ji} + \rho_k(a_j+D_i-a_i) & \text{if }i\in\mathcal{G}\cup\mathcal{W} \\ \lambda_{ji} + \rho_k(D_i - a_i) & \text{if }i\in\mathcal{D} \end{cases}

end for

end for

Project λ\lambda onto nearest point in Ωλ\Omega_\lambda

k:=k+1k:=k+1

end while